1. Field of the Invention
The present invention relates to electronic data retrieval devices, and more particularly to electronic digital logic devices having semiconductor mass storage capabilities by virtue of their data being stored in highly symmetrical arrays of diodes.
2. Prior Art
Most present day devices having mass storage capabilities rely on such moveable media as magnetic disks, optical compact disks, digital tape or the like. Some devices having large storage Capabilities  capabilities have utilized large numbers of read-only memory (ROM) devices.
Many read-only memory (ROM) devices have been disclosed having a wide variety of implementations. In many of these devices the bit storage means is accomplished through the application of gates or transistors. But, a subset of these ROM devices has accomplished the bit,  storage means through the use of a matrix of diodes, as was disclosed by Robb in U.S. Pat. No. 3,245,051. Many of these ROM devices is  include diode matrix storage means utilizing a set of conductors that act as selectors and a second orthogonal set of conductors that act as data outputs.
In U.S. Pat. No. 4,070,654, one set of generally parallel conductors acts as the Selection Input Lines and a second set of generally parallel conductors that is orthogonal to and overlapping with the first acts as the Digit Output Lines. A bit of information is represented at each point of intersection of the Selection Input lines with the Digit Output Lines by the presence or absence of a diode at that point, where the presence or absence of a diode distinguishes the logical state of the stored information bit at that point of intersection. A selection circuit selects one line of the Selection Input Lines such that the state of all of the Digit Output Lines is then controlled to the extent that each of those Digit Output Lines is connected to that selected Selection Input Line through a diode. All of the digit  Digit Output Lines are read in parallel. A disadvantage is that as the matrix is increased in size, the complexity of the selection logic that drives the selection circuits (such that one line is selected out of the many Selection Input Lines) grows exponentially. But as this matrix increases in size, so too will the number of Digit Output Lines that will have to be simultaneously supplied with current and that current will vary depending upon the state of the bits at those various locations. Also, as the number of simultaneously driven Digit Output Lines increases, some means of selecting the subset of desired data bits would have to be added.
In U.S. Pat. No. 4,661,927, some of the problems of the exponential growth in the complexity of the addressing circuitry and of the loading on the selected addressing lines are dealt with. Addressing is accomplished by using diode-transistor logic (DTL) for the input addressing. The transistors of the DTL selection circuits act as buffer-drivers between the address selection means and the bit storage means thereby providing the current needed to source a growing number of data bit output lines. However, the transistors in this DTL circuitry add complexity to the overall circuit which will reduce packing densities and add an additional problem—that of leakage currents in those transistors—that requires additional compensating circuitry that further reduces packing densities. The use of dummy diode loads for balancing data dependent loading variations reduces packing densities even further.
In U.S. Pat. No. 4,884,238, the problem of loading is dealt with by utilizing FET switches to disconnect all but the desired Digit Output line. The selected bit is present at the intersection of two selected orthogonal conducting lines. In this way, the number of bits simultaneously selected does not grow with the size of the array and the problem of loading can be controlled. But, such a design still requires a large number of FET transistors and the addressing means to control those FET transistors and the interconnection wiring to connect said addressing means with said FET transistors which will reduce packing densities. While the addressing means could be of the same DTL type to keep said addressing means small, the large number of buffering transistors to select the various conductive lines will remain large (at least one FET per conductive line and, on about half of the lines, two FET's). Furthermore, this inclusion of FET transistors may make the device subject to damage from static electrical discharges that might make it less practical for use in a consumer product where the consumer may handle these devices.
In U.S. Pat. No. 4,347,585, Eardley discloses a dual-addressed device wherein the selected diode is at the intersection of a column line and a row line (where the column lines are connected to the diodes' cathodes and the row lines are connected to the diodes' anodes) such that the voltage potential of one column line is lowered and the voltage potential of one row line is raised thereby forward biasing the diode, if any, at the point of intersection of the two lines. One of the features of this device over the prior art (as discussed in that patent) is the circuitry for the selection logic; Eardley discloses means for line selection comprising high speed transistor driver circuits. The disclosed device also requires two types of Schottky barrier diode devices. As a result, it is anticipated that the disclosed device will suffer from several problems, particularly when one attempts to scale up the device to extremely high storage densities. These problems may include transistor current leakage becoming noticeable as the number of transistors increases and device yields becoming reduced as the complexity of multiple semiconductor fabrication steps and nore  more complex device interconnect circuitry increases. These problems may prevent the kind of size scaling that could result in devices in the Gigabit range that would be necessary to create memory chips that could replace today's CD-ROMs.
As will be shown below, the Dual-addressed Rectifier Storage (DRS) Array comprised by the present invention solves many of the Problems  problems associated with the above mentioned inventions while sustaining high data packing densities by simultaneously using both orthogonal sets of conductors to address the data bits without the need for transistor switches on each conductive line. It does this by having a diode-logic addressing mechanism directly controlling the voltage levels on the conductive lines. Also, by extending the application of the diode array to perform the functions of addressing, storage, and bit sensing, symmetry is increased and this higher symmetry results in higher packing densities.
In U.S. Pat. No. 4,070,654, among others, a means is disclosed for programming the information into a semiconductor diode array by selectively etching away openings through the oxide layer that insulates the plurality of doped conductors from the orthogonal plurality of metalized conductors on the surface such that each opening enabled contact between the respective conductor of each plurality thereby forming a diode representing a toggled bit of stored information at that array location. The present invention discloses a means for constructing the semiconductor device up to the final metalization etch step before programming the data thereby enabling the programming of data to be performed much later in the manufacturing process.
Mass storage devices comprising moveable media such as magnetic disks, optical compact disks, digital tape, or the like, have motors and other mechanical parts that are prone to breaking or wearing out, can suffer audio disruption when subjected to vibrations, are too heavy to be carried during certain activities such as jogging, and consume significant electrical power (due to the operation of the mechanical components). Devices utilizing ROM chips are limited in their capacities due to the limited storage densities of present day ROM chips. The present invention eliminates or reduces all of these drawbacks because it uses DRS Arrays and, as a result, has the high storage densities of a CD-ROM without having mechanical parts.